1. Field of the Invention
The present invention relates to a solid-state image pickup device represented by a CMOS image sensor, and a camera system.
2. Description of Related Art
Recently, as a solid-state image pickup device (an image sensor) in place of a CCD, a CMOS image sensor has attracted attention.
The reason for this is that the CMOS image sensor solves problems inherent in the CCD in that manufacturing of CCD pixels requires a dedicated process, an operation for a plurality of power supply voltages, and the operation requires a combination of a plurality of peripheral ICs to highly complicate the system.
The CMOS image sensor has a plurality of effective merits in that: for the manufacturing, a manufacturing process similar to that of a general CMOS integrated circuit may be used; the CMOS image sensor may be driven by a single power-supply; and an analog circuit and a logical circuit using the CMOS process may coexist within an identical chip, thereby reducing the number of peripheral ICs.
For an output circuit of the CCD, a 1-channel (ch) output using an FD amplifier having a floating diffusion (FD) layer is mainly used.
On the other hand, the CMOS image sensor has an FD amplifier for each pixel. For output thereof, a column parallel outputting scheme, in which one row in a pixel array is selected, and pixels in the row are simultaneously read out in a column direction, is mainly used.
The reason for this is that it is difficult for the FD amplifier disposed in the pixel to provide a sufficient driving capability, and therefore, a reduction in data rate becomes necessary, and the parallel processing is advantageous.
A description is given of a general CMOS image sensor below.
FIG. 1 is a diagram showing one example of a pixel of the CMOS image sensor including four transistors.
A pixel 10 includes a photodiode 11 as a photoelectric conversion element, for example. For this one photodiode 11, the pixel 10 includes four transistors as active devices, which are a transfer transistor 12, an amplifier transistor 13, a selection transistor 14, and a reset transistor 15.
The photodiode 11 photoelectrically converts an incident light into an electric charge (in this case, an electron) having an amount which corresponds to an amount of the incident light.
The transfer transistor 12 is connected between the photodiode 11 and a floating diffusion FD. A gate (transfer gate) of the transfer transistor 12 is applied a drive signal through a transfer control line LTx, whereby the transfer transistor 12 transfers the photoelectrically converted electron at the photodiode 11 to the floating diffusion FD.
A gate of the amplifier transistor 13 is connected to the floating diffusion FD. The amplifier transistor 13 is connected via the selection transistor 14 to a signal line LSGN. A source follower is constituted by the amplifier transistor 13 and the constant current source 16 outside a pixel array.
An address signal is applied to a gate of the selection transistor 14 through a selection control line LSEL. When the selection transistor 14 is turned on, the amplifier transistor 13 amplifies a potential of the floating diffusion FD and outputs voltage corresponding to the potential to the output (vertical) signal line LSGN. A signal voltage outputted from each pixel through the signal line LSGN is outputted to a pixel signal read-out circuit.
The reset transistor 15 is connected between a power supply line LVDD and the floating diffusion FD. When a reset signal is applied to a gate of the reset transistor 15 through a reset control line LRST, the reset transistor 15 resets the potential of the floating diffusion FD to a potential of the power supply line LVDD.
More specifically, when the pixel is reset, the transfer transistor 12 is turned on to electrically clear electric charges accumulated in the photodiode 11. Subsequently, the transfer transistor 12 is turned off, the photodiode 11 converts a light signal into an electric charge, and accumulates the electric charge.
Upon reading out, the reset transistor 15 is turned on to reset the floating diffusion FD, the reset transistor 15 is turned off, and voltage of the floating diffusion FD at this time is outputted through the amplifier transistor 13 and the selection transistor 14. The output at this time is P-phase output.
Subsequently, the transfer transistor 12 is turned on to transfer the electric charges accumulated in the photodiode 11 to the floating diffusion FD, and the voltage of the floating diffusion FD at this time is outputted by the amplifier transistor 13. The output at this time is D-phase output.
When a difference between the D-phase output and the P-phase output is used as an image signal, not only a deviation of a DC component of the output for each pixel but also FD reset noise of the floating diffusion may be removed from the image signal.
These operations are performed simultaneously for each pixel of one row because the respective gates of the transfer transistor 12, the selection transistor 14, and the reset transistor 15 are connected in units of rows, for example.
Various proposals have been made regarding a pixel-signal reading out (output) circuit of the CMOS image sensor of the column parallel output type. One of the most advanced mode thereof is of type which is provided with an analog-digital converter (hereinafter, abbreviated as an ADC (Analog digital converter)) for each column and which extracts a pixel signal as a digital signal.
The CMOS image sensor including the column parallel ADC mounted thereon is disclosed, for example, in W. Yang, et al., “An Integrated 800×600 CMOS Image System”, ISSCC Digest of Technical Papers, pp. 304 to 305, February, 1999, or in Japanese Unexamined Patent Application Publication No. 2005-278135.
FIG. 2 is a block diagram showing a configuration example of a solid-state image pickup device (CMOS image sensor) including a column parallel ADC mounted thereon.
As shown in FIG. 2, a solid-state image pickup device 20 includes a pixel array 21 as an imaging unit, a vertical scanning circuit 22, a horizontal transfer scanning circuit 23, a timing control circuit 24; a group of ADCs 25, a digital-analog converter (hereinafter, abbreviated as a DAC (Digital-Analog converter)) 26, an amplifier circuit (S/A) 27, and a signal processing circuit 28.
The pixel array 21 includes a photodiode and an amplifier within the pixel, and is configured to arrange the pixels in a matrix manner, shown in FIG. 1, for example.
The solid-state image pickup device 20 includes a control circuit for successively reading out a signal of the pixel array 21. The control circuit includes the timing control circuit 24 for generating an internal clock, the vertical scanning circuit 22 for controlling a row address or row scanning, and the horizontal transfer scanning circuit 23 for controlling a column address or column scanning.
The group of ADCs 25 is formed by ADCs disposed in a plurality of columns. The ADCs includes comparators 25-1, counters 25-2, and latches 25-3. The comparators compare a reference voltage Vslop which is a ramp waveform (RAMP) obtained by varying stepwise a reference voltage generated by the DAC 26 and analog signals obtained via passing through vertical signal lines from the pixels for each row line. The counters count a comparing time. The latches hold a count result. The group of ADCs 25 has an n-bit digital signal conversion function and has each of the ADCs disposed for each vertical signal line (column line), thereby constituting column parallel ADC blocks.
Outputs of the respective latches 25-3 are connected to a horizontal transfer line 29 having a width of 2n bits, for example.
Further, 2n of amplifier circuits 27 corresponding to the horizontal transfer line 29 and a signal processing circuit 28 are disposed.
In the group of ADCs 25, analog signals (potentials Vsl) read out to the vertical signal lines are compared with the reference voltage Vslop (sloped waveform which changes to a linear shape having a certain gradient) at the comparators 25-1 disposed for each column.
At this time, the counters 25-2 disposed for each column similarly to the comparators 25-1 are operated, and when the reference voltages Vslop having a ramp waveform and counter values are changed on a one-to-one association basis, the potential (analog signal) Vsl of the vertical signal lines is converted into a digital signal.
The change of the reference voltage Vslop is to convert a change in voltage into a change in time, and the time is counted in a certain cycle (clock), thereby performing a conversion into the digital value.
When the potential Vsl of an analog electrical signal and the reference voltage Vslop cross, the outputs of the comparators 25-1 are inverted to stop input clocks of the counters 25-2. Thus, the AD conversion is completed.
After the above-described AD conversion period is ended, by the horizontal transfer scanning circuit 23, data held in the latches 25-3 are inputted to the signal processing circuit 28 via the horizontal transfer line 29 and the amplifier circuit 27. As a result, a two-dimensional image is generated.
As described above, the column parallel outputting process is performed.